1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to a semiconductor memory device employing a divided word line method. The present invention has particular applicability to static random access memories (SRAMs).
2. Description of the Background Art
A divided word line method is generally employed in semiconductor memories for driving or activating a word line having a long length of wiring at high speed. According to the divided word line method, conventional word lines are divided into a main word line for selecting a memory cell region and divided word lines for selecting individual memory cell rows. Description of a static random access memory (hereinafter referred to as "SRAM") will be given in the following as an example of a semiconductor memory employing the divided word line method.
FIG. 1 is a block diagram of a conventional SRAM employing the divided word line method. Japanese Patent Publication No. 63-8556 (1988) shows a block diagram similar to the one illustrated in FIG. 1. Referring to FIG. 1, a SRAM 100 includes memory cell array blocks 4a to 4d divided into four parts, local decoders 3a to 3d each connected to a corresponding memory cell array block, and a global decoder 1 connected through main word lines MWL1 to MWLn to respective local decoders 3a to 3d. Global decoder 1 drives or activates one of main word lines MWL1 to MWLn in response to an externally applied row address signal RA. Each of memory cell array blocks 4a to 4d includes memory cells arranged in rows and columns. Memory cells arranged in one row in each of memory cell array blocks 4a to 4d are connected to one divided word line WL. In addition, memory cells arranged in one column is connected to a bit line pair BL, BL.
SRAM 100 further includes Y gate circuits 7a to 7d each connected to corresponding one of memory cell array blocks 4a to 4d, sense amplifiers 8a to 8d each connected to corresponding one of memory cell array blocks 4a to 4d, and a column decoder 12. Sense amplifiers 8a to 8d amplify a small potential difference appearing between bit lines BL, BL. Column decoder 12 selectively turns on a switching transistor (not shown) in Y gate circuits 7a to 7d in response to an externally applied column address signal CA.
FIG. 2 is a block diagram illustrating another example of a conventional SRAM employing the divided word line method. A SRAM 200 illustrated in FIG. 2 is different from SRAM 100 illustrated in FIG. 1 in that a global decoder 1' is provided between memory cell array blocks 4b and 4c. Global decoder 1' is provided in the middle of memory cell array blocks 4a to 4d on a semiconductor substrate, so that it is possible to reduce the total length of wiring of main word lines MWL1 to MWLn and to achieve operation at a higher speed than that of SRAM 100 illustrated in FIG. 1.
FIG. 3A is a circuit diagram of a memory cell MC applicable to SRAMs 100 and 200 illustrated in FIGS. 1 and 2. FIG. 3B is a circuit diagram of a memory cell MC' applicable to SRAMs 100 and 200 as a substitute for memory cell MC illustrated in FIG. 3A.
FIG. 4 is a circuit diagram of local decoders 3a and 3b illustrated in FIG. 1. Referring to FIG. 4, local decoder 3b, for example, includes divided word line driving circuits each driving or activating corresponding one of divided word lines WL1, WL2, . . . . A divided word line driving circuit 30 is implemented with an NAND gate and an inverter and drives word line WL1. A global decoder 1 decodes more significant bits R'A2 to RAm of an externally applied row address signal to selectively drive main word lines MWL1, MWL2 . . . . A two-bit decoder 9 referred to as "V decoder" decodes less significant two bits RA0 and RA1 of the row address signal to selectively drive signal lines SL1 to SL4. A local decoder selecting circuit 13 decodes predetermined two bits CAj and Caj+1 of an externally applied column address signal to apply a selecting signal for selecting one of memory cell array block 3a and memory cell array block 3b to local decoder controlling circuits 10a and 10b. Each of local decoder controlling circuits 10a and 10b is responsive to the selecting signal applied from local decoder selecting circuit 13 for applying output signals SL1 to SL4 provided from V decoder 9 to corresponding one of memory cell array blocks 3a and 3b.
It is pointed out that one output signal line of global decoder 1, main word line MWL1, for example, selects memorycell regions MAa and MAb. Specifically, activation of main word line MWL1 causes memory cell regions MAa and MAb accessible through local decoders 3a and 3b to be determined.
Now, operation of the circuit illustrated in FIG. 4 will be described. A case where divided word line WL1 in memory cell region MAb is driven will be described as an example in the following. Global decoder 1 is responsive to more significant bits RA2 and RAm of a row address signal for selectively activating main word line MWL1. On the other hand, V decoder 9 is responsive to less significant bits RA0 and R1 of the row address signal for selectively activating output signal line SL1. Local decoder selecting circuit 13 is responsive to jth and j+1th column address signals CAj and CAj+1 for generating a selecting signal for selecting local decoder controlling circuit 10b. As a result, two input signals at a high level are applied only to the NAND gate in divided word line driving circuit 30. Accordingly, divided word line WL1 is driven or activated by driving circuit 30.
FIGS. 5A, 5B, and 5C are circuit diagrams illustrating conventional divided word line driving circuits 31, 32, and 33. Each of circuits 31, 32 and 33 is applied as divided word line driving circuit 30 illustrated in FIG. 4. One and the other of output signals of global decoder 1 and local decoder controlling circuit 10b illustrated in FIG. 4 are applied respectively as input signals S1 and S2 to each of circuits 31 to 33.
Referring to FIG. 5A, divided word line driving circuit 31 includes PMOS transistors 111 and 112, NMOS transistors 211 and 212, and an inverter 11, and first and second supply potentials Vcc and V.sub.EE are applied thereto. Transistors 112 and 211 are connected so that their gates receive first input signal S1. Transistors 111 and 212 are connected so that their gates receive second input signal S2. The output of inverter 11 is connected to a divided word line WL.
Referring to FIG. 5B, divided word line driving circuit 32 includes PMOS transistors 113 and 114 and NMOS transistors 213 and 214, and first and second supply potentials Vcc and V.sub.EE are applied thereto. Transistors 113 and 213 are connected so that their gates receive first input signal S1. Transistors 114 and 214 are connected so that their gates receive second input signal S2.
Referring to FIG. 5C, divided word line driving circuit 33 includes an NMOS transistor 201 as a transfer gate, a PMOS transistor 102 for charging the output electrode of transistor 201, and an inverter 11 for driving a word line WL. First input signal S1 is applied to the gate of transistor 201. Second input signal S2 is applied through transistor 201 to the input of inverter 11. The gate of transistor 102 is connected to the second supply potential V.sub.EE, so that transistor 102 is always brought to ON state. The circuit illustrated in FIG. 5C is disclosed in, a paper titled "A 15ns 4Mb CMOS SRAM." (ISSCC DIGEST OF TECHNICAL PAPERS, pp. 126-127; Feb. 1990) by Aizaki S., et. al.
FIGS. 6A to 6E are circuit diagrams of inverters applicable in a divided word line driving circuit. Specifically, inverters 11a to 11e illustrated in FIGS. 6A to 6E are applicable as inverter 11 illustrated in FIG. 5A or FIG. 5C.
Following problems are pointed out with respect to conventional divided word line driving circuits 31, 32 and 33. The number of transistors required for constituting driving circuit 31 illustrated in FIG. 5A is larger in comparison with those for the other driving circuits 32 and 33. Specifically, even if inverter 11a illustrated in FIG. 6A is used as inverter 11, six transistors in total are required. This means that the region occupied by local decoders on a semiconductor substrate is increased.
Divided word line driving circuit 32 illustrated in FIG. 5B is implemented with four transistors, so that the occupied region on a semiconductor substrate is smaller than that of circuit 31 illustrated in FIG. 5A. However, in order to obtain the same word line driving capability as that of circuit 31 illustrated in FIG. 5A, it is necessary to increase the gate width of each of transistors 113, 114, 213, and 214. The gate capacitance of each of transistors 113, 114, 213, and 214 is increased, so that it is necessary to considerably increase the load driving capability of the circuits which drive divided word line driving circuit 32, i.e. global decoder 1 and local decoder controlling circuits 10a and 10b.
In a case where inverter 11a illustrated in FIG. 6A is applied, divided word line driving circuit 33 illustrated in FIG. 5C requires four transistors. In addition, inverter 11 for driving word line WL is provided, so that it is not necessary to increase the gate width of each of transistors 102 and 201. Accordingly, it is possible to obtain word line driving capability for driving a divided word line without increasing the load driving capability of global decoder 1 and local decoder controlling circuits 10a and 10b. However, problems as described in the following have arisen.
In divided word line driving circuit 33 illustrated in FIG. 5C, rising of an input signal S3 of inverter 11 is caused only by transistor 102. In order to make rising of input signal S3 more rapid, it is necessary to reduce the on resistance by setting the gate width of transistor 102 larger. However, reducing the on resistance of transistor 102 delays falling of signal S3 and causes increase in current consumption. Accordingly, it is pointed out that the on resistance of transistor 102 must be set to an appropriate value which is not so low in view of a required operation speed and current consumption.